1. Field of the Invention
This invention pertains to the field of microelectronic chip fabrication for logic, memory, communication and microcontroller applications. More particularly, this application pertains to the use of a support structures to enable the integration of ultra low dielectric constant (K) materials in semiconductor devices.
2. Description of the Prior Art
The operating speeds of silicon integrated circuits are increasing at phenomenal rates to meet aggressive performance demands in computing, communication and microcontroller applications. This in turn necessitates that signal propagation delays in the wiring that is used to interconnect the circuits on a chip be reduced so that performance is not unduly limited or hampered by interconnect delays. Interconnect delays in chips occur due to the RC time constants wherein R is the resistance of the on chip wiring and C is the effective capacitance between the signal lines and the surrounding conductors in the multilayer interconnection stack.
Interconnect capacitance can be reduced by reducing the dielectric constant, K, of the insulating medium that surrounds these lines. Hence, there has been a significant effort to identify and use low K insulators in interconnect structures. A whole gamut of insulator materials including fluorinated silica, polymers with and without fluorination, amorphous teflon-like polymers, and aerogels made of porous silica have been proposed as possible low K materials for this purpose.
There are several practical difficulties in integrating the low K dielectric materials in such a wiring structure. First, the physico-chemical properties of many of these low K materials are not optimal for the chemical-mechanical polishing process. For example, most of the polymer materials are too soft and erode at too a rapid rate during chemical-mechanical polishing to allow good control over the inlaid layer thickness. Some of these issues can be contained by applying a hard cap layer over the dielectric to act as a chemical-mechanical polishing stop layer, however this requires additional processing and the difficulty of ensuring compatibility of the low K material with the processing of this additional layer. Second, most of the low K polymers degrade under thermal excursions to temperature at or above 400° C. Hence, they are not suitable for the device interconnection application because they cannot withstand device damage inflicted during an annealing process severely restricting the choice of dielectric that can be used for this purpose. Last, porous inorganic dielectrics such as aerogels are mechanically weak (i.e. porous and brittle) and, therefore, unlikely to withstand a multilayer build process of repeated metal deposition and chemical-mechanical polishing.
A method taught by Chang et al., U.S. Pat. No. 5,559,005, solves this problem with a process in which a first layer is fabricated of aluminum-based interconnect wiring, comprising an insulator (silicon dioxide) and a stud layer deposited into the vias in the insulator. A second interconnect wiring layer of aluminum alloy is then deposited and patterned on top of the first layer. The insulator is removed from between the metal features by an etching process. The structure is then either fully or partially filled with a lower dielectric constant material, and a passivation layer is deposited over the resulting structure. A net lowering of the dielectric constant is achieved by this process due to the replacement of the oxide material with a lower K insulator. While this method, in principle, can achieve a uniform and lower K value dielectric, the partially voided low K dielectric structure does not yield a uniform or predictable value of effective K due to the fact that the presence or absence of voiding depends on a myriad of factors including the size, spacing and aspect ratio of the metal features and, for solution-based insulator depositing, the viscosity and the solvent content of the filling insulator precursor solution. This complicates the task of designing circuits since circuits require that the effective dielectric constants be precisely known and maintained within a narrow range to achieve minimized delay tolerances and hence improved chip performance.
A method taught by Buchwalter et al., U.S. Pat. No. 6,148,121 describes a process in which air, having the lowest dielectric constant, is used as the intralevel dielectric. A multilayer interconnect wiring structure is fabricated by methods and materials currently known in the state of the art of semiconductor processing; the intralevel dielectric between adjacent metal features is then removed by a suitable etching process; the etched structure is annealed to remove plasma damage; a thin passivation coating is applied over the exposed etched structure; an insulating cover layer is laminated to the top surface of the passivated metal features; an insulating environmental barrier layer is optionally deposited on top of the cover layer; and vias are etched in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts. The device is completed by fabricating terminal input/output pads. While this method obviates issues such as processablity and thermal stability associated with low dielectric constant materials by avoiding their use, the method requires additional processing steps.
The process of the present invention accomplishes the above-mentioned goals in an efficient and cost-effective process that obviates the additional processing steps of patterning, etching and alignment. The instant invention, by adapting contact printing, rather than convention lithography, to form a support structure provides a more practical and economical solution for the integration of ultra low K dielectrics. The use of contact printing, a high-through-put high-resolution printing technique as an alternative to lithography provides several benefits not provided by conventional chip fabrication methods. First, contact printing addresses issues in the science of manufacturing at scales below 200 nm. Second, contact printing enables completely novel approaches to semiconductor chip fabrication. Pattern transfer is direct, thereby enabling novel strategies of assembling semiconductor devices. A further benefit provided by the contact printing process in the manufacture of semiconductor devices is that the alignment of the support structure is not critical to the contact printing process.